1. Field of the Invention
The present invention relates to a memory macro, and in particular to a memory macro composed of a plurality of memory cells such an SRAM or the like.
2. Description of the Related Art
FIG. 11 shows an arrangement of a generally known memory macro. A plurality of memory macros 10 are mounted on a semiconductor integrated circuit 1 or the like as shown in FIG. 11 and store access data from logical circuits 20. Also, the memory macro 10 is supplied with a voltage (hereinafter, power voltage) equivalent to a potential difference between a power potential (on a high potential end of the power voltage) VDD and a reference potential (on a low potential end of the power voltage) VSS from an outside power control circuit 30.
Also, the memory macro 10 is composed of memory cells 100_11-100_mn (hereinafter, occasionally represented by a reference numeral 100) arranged in “m” rows and “n” columns, word line drivers 200_1-200_m (hereinafter, occasionally represented by a reference numeral 200) connected to the memory cells 100 of the same row by a word line WL, sense/write amplifiers 300_1-300_n (hereinafter, occasionally represented by a reference numeral 300) connected to the memory cells 100 of the same column by bit lines BL, and an address decoder 400 controlling the word line drivers 200 according to an address (not shown) inputted from the logical circuit 20.
As shown in FIG. 12, each of the memory cells 100_11-100_mn forms a flip-flop circuit with a CMOS inverter INV1 where drain electrodes D and gate electrodes G of a loading P channel FET TP1 and those of a driving N channel FET TN1 are mutually connected, and a CMOS inverter INV2 where drain electrodes D and gate electrodes G of a loading P channel FET TP2 and those of a driving N channel FET TN2 are mutually connected. Both source electrodes S and both back gate electrodes BG of the loading P channel FETs TP1 and TP2 are connected to the power potential VDD through a power line VL1. Both source electrodes S and both back gate electrodes BG of the driving N channel FETs TN1 and TN2 are connected to the reference potential VSS through a power line VL3.
Also, the common drain electrodes D of the CMOS inverters INV1 and INV2 are connected to the word line WL and a pair of the bit lines BL through source electrodes S and drain electrodes D of transferring N channel FETs TN3 and TN4. Both gate electrodes G and both back gate electrodes BG of the transferring N channel FETs TN3 and TN4 are respectively connected to the word line WL and the reference potential VSS.
In operation, it is now supposed that the word line drivers 200_1-200_m having been controlled by the address decoder 400 shown in FIG. 11 select only one of the word lines WL1-WLm connected thereto. Namely, as shown in FIG. 12, the word line driver 200_1 makes the word line WL1 a high level H and the other word line drivers 200_2-200_m make the word lines WL2-WLm a low level L.
At this time, the transferring N channel FETs TN3 and TN4 within the memory cells 100_11-100_1n where the gate electrodes G are connected to the word line WL1 are turned on, so that channels are formed between the respective source electrodes S and drain electrodes D. Then, data held by the memory cells 100_11-100_1n is to be read or updated (written) according to logical levels supplied through the bit lines BL from the sense/write amplifiers 300 shown in FIG. 11 (hereinafter, this state is called “access state”).
On the other hand, since the transferring N channel FETs TN3 and TN4 within the memory cells 100_21-100_mn where the gate electrodes G are connected to the word lines WL2-WLm are now off, neither reading nor writing the data to the memory cells 100_21-100_mn is performed, so that the data is held (hereinafter, this state is called “hold state”).
Recently, with increases of the number of memory macros mounted on the semiconductor integrated circuit and the number of memory cells included in each memory macro, power consumption due to a leak current of the memory macro has occupied a large proportion of the entire circuit power consumption.
Prior art examples [1] and [2] indicating technologies to address this problem will be described as follows: